Photon Reverse Engineering


Analog Circuit Description

I have not done a complete reverse engineering of the Photon system, but enough to give a basic description of what is going on. Double-click on any picture to see a full size image.

The pickup LEDs are run in series with one current limiting resistor on the pickup PCB. Therefore if one emitter fails, all of them go dark. Measuring the forward voltage using the diode/continuity setting of a simple DVM without power applied to the pickup system will reveal the failed part. It will have no voltage drop while the functioning ones run about 1.4 volts.

The emitter of all the pickup phototransistors is tied to ground while each collector connects to the pickup interface board where there is a sensitivity trim pot for each detector. This signal is then sent through the 15 pin D cabling to the main box.

Signal with string optimally aligned

Signal with string optimally aligned to the pickup optical path

Signal From Pickup

Signal with string aligned below the pickup optical path

Each string signal is AC coupled to eliminate the DC signal from the photo detector and connected to one half of a CA3280 dual Operational Transconductance Amplifier or OTA. There are a total of three 3280s in the controller.

The following paragraph is excerpted from the Intersil spec. sheet for the CA3280 for reference.

"The CA3280 has all the generic characteristics of an operational voltage amplifier except that the forward transfer characteristics is best described by transconductance rather than voltage gain, and the output is current, not voltage. The magnitude of the output current is equal to the product of transconductance and the input voltage. This type of operational transconductance amplifier was first introduced in 1969, and it has since gained wide acceptance as a gateable, gain controlled building block for instrumentation and audio applications, such as linearization of transducer outputs, standardization of widely changing signals for data processing, multiplexing, instrumentation amplifiers operating from the nanopower range to high current and high speed comparators."

The transconductance (i.e. gain) of the OTA is controlled by a current input on pins 1 and 8. The Photon Pickup Sensitivity knob on the front panel adjusts the signal gain at this point.

From there, the signal is routed to a LM1458 dual op amp which amplifies the signal. Section A is the amplifier and section B appears to be an inverter. Next in line is a National MF10 Universal Monolithic Switched Capacitor Filter. This is a dual filter and one filter is used for each string so there are three devices in the unit. This is a tuned low pass filter and it doesn't appear that there is any active adjustment of the filter based on the note played.

After Low Pass

Signal after low pass filter

The filtered signal, which is fairly sinusoidal at this point, is then fed to an LM324 quad OP AMP. The B section of the 324 amplifies the signal from the low pass filter by about 2.  The A section then further amplifies and clips the signal to create a square wave.


Signal after squaring

Section D of the LM324 does heavy integration to extract the envelope of the signal.


Envelope signal after integration

Once squared the signal is run to a series of gates and counters.

The squared string signal output of the LM324 is connected to both inputs (pins 8 and 9) of gate "C" of a CD4011 quad NAND. This inverts the signal. Don't know why this is done. Pin 10, the output of gate "C", is therefore a 5 volt squared string signal.

Pin 10 4011

CD4011 Pin 10. String signal squared at logic levels.

The B section of the 4011 has an approximately 2 MHz  high frequency clock signal on one input (pin 5) and a high on the other input (pin 6). The clock signal at pin 5 does not swing fully over 5 volts and this gate serves to improve the quality of the clock signal.

The "A", "B" and "D" gates in the 4011 serve to gate the clock signal going to the CLK input of the three timers in an 82C54 dual programmable interval timer. "A" is tied to timer 0, "B" is tied to timer 2 and "D" is tied to timer 1. The gate signals come from the OUT pins of the 82C54. We'll look at this more in a couple paragraphs.

The squared string signal is run to the CLK input (pin 14) of a CD4017 5-stage divide by 10 Johnson counter/divider. It is configured to divide the string input by 3 by feeding back OUTPUT 3 (pin 7) to the RESET input (pin 15).

Counter Out

CD4017 Pin 3 “OUTPUT 0” (top trace)  CD4017 Pin 14 “CLOCK IN” (bottom trace)

The divide-by-3 string signal is connected to the GATE inputs (pins 11, 14 and 16) of a 82C54 programmable interval timer. The 82C54 has three independently programmable and functional 16-bit counters, each capable of handling clock input frequencies of up to 8MHz. Each timer has a gate input, clock input and a counter output. The input clock is 2.0 MHz and is the same for every string. The gate input is the string frequency divided by 3 by the 4017 counter/divider. Therefore each counter will count the number of clock cycles between rising edges of the divide-by-3 string signal, indicating the frequency of the string.

The OUT pins of the timers are tied to the 4011 NAND gates and each serves to control the 2.0 MHz clock signal running to its respective CLK input. As we'll see, the operation of the OUT pins is not easy to discern. They do not strictly follow the "on" time of the string.

There are several different programmable operating modes for the timer and it isn't clear to me how each section is programmed or used. It's possible that Mode 5, "Hardware Triggered Strobe" mode is used as in this mode counting is begun by the rising edge of GATE (the string signal). If a new count is written during counting, the current counting sequence will not be affected. If a trigger occurs after the new count is written but before the current count expires, the counter will be loaded with a new count on the next CLK pulse and counting will continue from there. When the initial count has expired, OUT will go low for one CLK pulse and then go high again. Therefore the timer will count the number of clock signals between every third string period which makes sense. Why three timers are needed isn't known. I also don't see the OUT pins going low in a regular fashion relative to a timeout of the counter.

As I said, this all makes sense except for the low E string on a guitar, which is 82.4 Hz . Since the string frequency is divided by 3, the low E input to the timer has a 36.4ms period. Divided by the 0.5us clock frequency this makes for 72,816 clock cycles which is beyond the capability of a 16 bit timer so I'm missing something here. I verified that the divide by 3 signal is tied to the timer but spent most of the time investigating the high E string circuit since it was easier to probe.

Lo E divided by 3 = 36.4ms / 0.5us = 72,816 clock cycles

Hi E divided by 3 = 9.10ms / 0.5us = 18,204 clock cycles.

Hi E 24th fret divided by 3 = 2.27ms / 0.5us = 4,551 clock cycles.

The three different sections are apparently programmed by the Z80 microprocessor to time different events of the string, perhaps the initial frequency, the sustained frequency then a final cutoff frequency. Don't know. Below are some scope pictures showing the relationship of the Hi E string to the different timer outputs.

Top Trace (trigger) is 82C54 OUT 0
Bottom trace is 82C54 OUT 1

Out 0 Out 1 Plucked String

Pluck string then mute

Out 0 Out 1 Tapped String

Rapidly tapping the string

I don't see much of a relationship here.

For the images below, the Top Trace (trigger) is the squared string signal and the bottom trace is the 82C54 OUT 1.

Pluck Damp then Tap

Pluck the string then mute it, then tap. OUT 1 (bottom trace) goes low when the string is muted

Pluck then Decay

 Pluck then allow to decay. OUT 1 (bottom trace) goes low a bit after the string fades out

String Pluck then mute

Pluck then mute. Again, OUT 1 goes low when the string dies, but not every time.

Very Gentle Pluck

Very gentle pluck

Pluck, gentle damp then pluck and firm damp

Pluck, gentle mute then pluck and firm mute.

Only the firmer damping brought OUT 1 low, even though the string dies out with the gentle damping.

I did many other trials to try and determine what was happening with the OUT signal from the timer and couldn't figure it out. I could pluck a string, let it die out and never see any of the OUT signal change. Then I can gently tap the string enough to create  "thump" but not enough to create any pitch from the string, and OUT would go low. Not sure it matters but I am curious what was going on.

I did not reverse engineer the input circuit after the photodetector. This would be useful to know to allow the use of other pickups. The CA3280 is the first IC in the signal path and I there has to be a pull up resistor to provide current for the photodetectors since their emitters are tied to ground. There must be a fairly large capacitor in series for AC coupling.

I also didn't spend much time comparing the different string circuits, except to confirm that the same 2MHz clock is used on all the timers and that the low E string uses the divide by 3 output from the 4017 divider to drive the gate inputs of the 82C54 timer. As I said before, this doesn't really make sense as the period of the guitar low E not to mention a bass low E seems to be beyond the counting period of the 16 bit timer running at 2MHz.

A few other notes...

A SCN2651 Programmable Communications Interface chip on the main board generates the MIDI interface. An ADC0808 8 input 8 bit analog to digital converter sits underneath the microprocessor board. There is more glue logic on the main board but I haven't bothered to try and reverse engineer this or the function of the 8 bit ADC but I'm guessing it probably is used for string amplitude/envelope measurement.

A separate processor board is mounted above the main board and has a Z80 running at 4MHz. There's a 6264 8Kx8 static RAM backed up by a CR2032 lithium button battery. There is also an Intel P8254 programmable interval timer similar to the ones used to measure the string frequencies but it does not appear to be tied in with string measurement at all. There's also a 20 pin .3" center dip with a part number label on it. Probably a gate array of some sort.

Link to pictures of the PCBs: PCB Pictures